1. Field of the Invention
The present invention relates to a digital convergence unit for adjusting the convergence of a color television receiver by converting correction data in accordance with changes in the horizontal and vertical frequencies, screen aspect, and horizontal and vertical amplitudes, even if they change after the dynamic convergence has been adjusted.
2. Description of the Related Art
In general, in a projection type color picture receiver which projects expanded color pictures on a screen by using three projection tubes that emit three primary colors, mis-convergence may occur on the screen due to different incident angles of the color rays emitted onto the screen from the respective projection tubes.
The three primary colors, can be registered, or converged, by adjusting the waveform and magnitude of a convergence correction signal, which is an analog signal synchronized with the horizontal and vertical scanning periods. This method, however, has a problem in its convergence precision. In order to solve this problem, there are various proposals for digital convergence units which can provide high convergence precision, such as one that can treat various types of signal sources as disclosed in JP-A-60-130288, or one that can treat various screen aspect ratios as disclosed in JP-A-62-11388.
A conventional digital convergence unit will be explained below. FIG. 11 is a block diagram showing the conventional digital convergence unit. This unit produces on the screen a convergence correction pattern such as the cross-hatch pattern shown in FIG. 12, digitally writes convergence correction quantity data for each adjusting point in a frame memory, reads this data out of the memory, interpolates the data between the adjusting points, and converts it from digital to analog, thereby to produce a correction signal for position adjustment of the primary color components over the entire screen. Referring to FIG. 11, 1 designates a pattern picturing circuit, 2 designates a horizontal synchronizing signal, 3 designates a horizontal address counter circuit, 4 designates a vertical synchronizing signal, 5 designates a vertical address counter circuit, 6 designates a read address generation circuit, 7 designates a write address generation circuit, 8 designates a control panel, 9 designates a data reversible counter, 10 designates a frame memory control circuit, 11 designates a frame memory, 12 designates a vertical interpolation circuit, and 13 designates a D/A conversion circuit.
Next, operation of the above conventional example will be explained. First, as shown in FIG. 12, a cross-hatch signal is emitted by the pattern picturing circuit 1 to display a cross-hatch pattern on the screen. This cross-hatch pattern includes seven horizontal lines and nine vertical lines, for example. A signal for the horizontal direction in the pattern is produced by supplying the horizontal synchronizing signal 2, which is synchronous with the scanning of the screen, to the horizontal address counter circuit 3. Horizontal address counter circuits comprises a PLL (Phase Lock Loop) circuit and a frequency dividing circuit. A vertical direction signal for the pattern is produced by the vertical address counter circuit 5, which is reset by the vertical synchronizing signal 4, and is supplied to the pattern picturing circuit 1 to display the vertical lines on the screen. Next, a cursor key (not shown) on the control panel 8 is used to select a cross point of the cross-hatch signal to be corrected (hereinafter referred to as an adjusting point) and a color (e.g. red) to be corrected. The address of an adjusting point selected by the cursor key is stored in the write address generation circuit 7 and is supplied to the frame memory 11 through the frame memory control circuit 10. The data to be corrected at the adjusting point designated by the cursor key is read from the frame memory 11 and is written in the data reversible counter 9. Further, a write key (not shown) on the control panel 8 is operated to either increase or decrease the content of the data reversible counter 9 to correct the data before it is returned to the frame memory 11.
The reading of the convergence correction data written in the frame memory 11 will now be explained. Horizontal and vertical addresses corresponding to each of the adjusting points on the screen are produced by the horizontal address counter circuit 3 and the vertical address counter circuit 5, which respectively receive the horizontal synchronizing signal 2 and the vertical synchronizing signal 4. The signals 2 and 4 are in synchronism with the scanning period of the screen. The horizontal and vertical addresses are supplied to the read address generation circuit 6, and then applied to the frame memory 11 through the frame memory control circuit 10, thereby to read the correction data at each adjusting point. The frame memory 11 stores correction data only for the positions corresponding to each of the adjusting points. Therefore, for the correction between adjusting points in the vertical direction, interpolation is performed by the vertical interpolation circuit 12. The vertical interpolation circuit 12 comprises a subtraction circuit, a coefficient ROM, a multiplication circuit, and an addition circuit, etc. The vertical interpolation circuit 12 performs an interpolation operation, for example, by using the subtraction circuit to obtain the difference between two adjusting points (i.e. a point 14 in the second row and a point 15 in the third row) based on the correction data, using the multiplication circuit to multiply the difference by a weighting coefficient for each scanning line, the weighing coefficient being written in the coefficient ROM in advance, and using the addition circuit to add the result to the correction data for the point 14 in the second row. The output of the vertical interpolation circuit 12 is converted into an analog quantity by the D/A conversion circuit 13, to obtain a stepped wave shape signal. A signal between the adjusting points in the horizontal direction is adjusted such that the correction quantity at the adjusting points in each line is smoothed out by a low pass filter (not shown) and is supplied to the convergence yoke after being amplified.
As described above, according to the conventional method, each adjusting point can be corrected independent of the others, to ensure convergence correction with high precision.
When the horizontal and vertical frequencies, screen aspect, and horizontal and vertical amplitudes change, adjustments are made in the same manner as described above.
Thus, according to the conventional method, each adjusting point can be corrected independently, and corrections can also be performed for signal sources with different horizontal and vertical frequencies, screen aspects and horizontal and vertical amplitudes, so that convergence correction can be performed with high precision.
However, when the horizontal and vertical frequencies, screen aspect, and horizontal and vertical amplitudes change, positional deviation in the digital convergence adjusting pattern such as cross-hatches may occur on the screen, so that digital convergence correction data cannot be shared. As a result, convergence correction must be repeated each time for the number of images corresponding to the changed patterns, which requires that all the convergence correction data be held.
Although there is an alternative method for sharing data by changing the number of adjusting points by making the number correspond to an aspect ratio, this method involves complex processing in the address system such as for memory writing because the adjusting points change. Therefore, there is the problem that the scale of the circuit needs to be very large.